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NXP Semiconductors /MIMXRT1021 /ADC_ETC /TRIG3_CTRL

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Interpret as TRIG3_CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SW_TRIG)SW_TRIG 0 (TRIG_MODE)TRIG_MODE 0TRIG_CHAIN 0TRIG_PRIORITY 0 (SYNC_MODE)SYNC_MODE

Description

ETC_TRIG Control Register

Fields

SW_TRIG

Software write 1 as the TRIGGER. This register is self-clearing.
TRIG_MODE

TRIG mode register. 1’b0: hardware trigger. 1’b1: software trigger.
TRIG_CHAIN

TRIG chain length to the ADC. 0: Trig length is 1; … 7: Trig length is 8;
TRIG_PRIORITY

External trigger priority, 7 is highest, 0 is lowest .
SYNC_MODE

TRIG mode control . 1’b0: Disable sync mode; 1’b1: Enable sync mode

Links

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Register License

Copyright 2016-2020 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data